The present invention relates generally to matrix addressing arrangements and, more particularly, to improvements in a matrix addressing arrangement especially suitable for use as part of matrix addressed flat panel display or other such device requiring matrix addressing.
A representative matrix-addressed flat panel display in the prior art is described in U.S. Pat. No. 4,857,799, which is incorporated herein by reference. The display described there includes a transparent face plate mounted over and spaced from a backing plate so as to define an interior chamber. The transparent face plate carries on its internal surface a thin coating or film of electrically conductive transparent material, such as indium tin oxide, which serves as an accelerator plate and a phosphor-coating. The internal surface of the backing plate supports a matrix array of field emission cathodes in confronting relationship with the face plate and suitable address means for energizing selected ones of the field emission cathodes, thereby causing the energized cathodes to bombard the phosphor-coated face plate which, in turn, results in the emission of visible light. It is this light that is viewed by the observer through the face plate, that is, on the screen of the flat panel display.
Still referring to U.S. Pat. No. 4,857,799, the address means forming part of the display illustrated there includes: a lower planar array of spaced apart, parallel, electrically conductive row leads which are formed on the top surface of the displays backing plate and which support the matrix array of field emission cathodes; an upper planar array of spaced-apart, parallel, electrically conductive column leads located above and spaced from the lower array of leads and field emission cathodes such that the upper leads extend normal to the lower leads, crossing the latter immediately above the cathodes; and a layer of dielectric material disposed between the upper and lower arrays of electrically conductive leads. This combination of components is diagrammatically illustrated in FIG. 1.
As seen in FIG. 1, the backing plate, which is generally indicated at 10, supports the lower electrically conductive row leads, one of which is designated by the reference numeral 12. Each lower row lead 12 supports one or more field emission cathodes 14. Spaced above the row leads 12 are the column leads, one of which is shown at 16. Between these leads is a layer 18 of suitable dielectric material. Note specifically that in a typical matrix addressing arrangement, the column leads extend normal to the row leads and, at each juncture where these leads cross, one or more of the field emission cathodes are positioned within cooperating apertures, one of which is indicated at 20 in FIG. 1. Each of these apertures 20 extends through the upper column leads 16 and also through dielectric layer 18.
While the matrix-addressed flat panel display disclosed in U.S. Pat. No. 4,857,799 is generally satisfactory for its intended purpose, there are certain aspects of the display which can be improved upon. For example, if the dielectric layer 18 illustrated in FIG. 1 is too thin, defects in this layer could result in electrically shorting together a row lead with a crossing column lead, as diagrammatically illustrated in FIG. 1, at 22. Moreover, the closer the column electrodes are to the row electrodes, the greater the capacitance is between the two, thereby increasing the RC time constant associated with the addressing operation of the display. If this RC time constant is too large, the addressing operation may be too slow for the intended purpose of the display. One way to overcome these disadvantages is to increase the thickness of dielectric layer 18. However, in the typical process of making flat panel displays utilizing a single deposition step to form its field emission cathodes, this would place the column leads, which serve as gates, too far from the tips of the field emission cathodes. A solution to this problem is to form the cathodes by means of a double deposition process, as described in co-pending U.S. patent application Ser. No. 472,336, filed Jan. 29, 1990 and incorporated herein by reference.